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cat25c32/64 32k/64k-bit spi serial cmos eeprom features 10 mhz spi compatible 1.8 to 6.0 volt operation hardware and software protection low power cmos technology spi modes (0,0 &1,1) commercial, industrial and automotive temperature ranges 1,000,000 program/erase cycles 100 year data tetention self-timed write cycle 8-pin dip/soic, 14-pin tssop and 20-pin tssop 64-byte page write buffer block write protection C protect 1/4, 1/2 or all of eeprom array pin configuration block diagram ? 2004 by catalyst semiconductor, inc. characteristics subject to change without notice description the cat25c32/64 is a 32k/64k-bit spi serial cmos eeprom internally organized as 4kx8/8kx8 bits. catalysts advanced cmos technology substantially reduces device power requirements. the cat25c32/ 64 features a 64-byte page write buffer. the device operates via the spi bus serial interface and is enabled though a chip select ( cs ). in addition to the chip select, the clock input (sck), data in (si) and data out (so) are required to access the device. the hold pin may be used to suspend any serial communication without resetting the serial sequence. the cat25c32/64 is designed with software and hardware write protection features including block write protection. the device is available in 8-pin dip, 8-pin soic, 14-pin tssop and 20-pin tssop packages. doc no. 1001, rev. g dip package (p, l) tssop package (u20, y20) soic package (s, v) sense amps shift registers spi control logic word address buffers i/o control e 2 prom array column decoders xdec high voltage/ timing control so status register block protect logic control logic data i n storage si cs wp hold sck so wp cs v cc hold sck si 1 2 3 4 8 7 6 5 v ss v ss so wp v cc hold sck si 1 2 3 4 8 7 6 5 cs tssop package (u14, y14) cs wp hold vcc nc nc nc nc so nc nc v ss sck si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc nc cs wp hol d hol d vcc nc nc nc nc nc nc so nc nc so v ss sck si 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pin functions pin name function so serial data output sck serial clock wp write protect v cc +1.8v to +6.0v power supply v ss ground cs chip select si serial data input hold suspends serial input nc no connect h a l o g e n f r e e tm l e a d f r e e
2 doc. no. 1001, rev. g 7&&:; v cc = +1.8v to +6.0v, unless otherwise specified. . # , 1#%" # )& 1$& >& ) , ,")* "), i cc1 power supply current 10 ma v cc = 5v @ 10mhz (operating write) so=open; cs=vss i cc2 power supply current 2 ma v cc = 5.0v (operating read) f clk = 10mhz i sb (5) power supply current 1 ? ??? ? ?????
3 doc. no. 1001, rev. g . # , =!!a = a = a &'=&= &=&= &=&= , <. )& >& )& >& )& >& : ")* "), t su data setup time 50 50 20 ns t h data hold time 50 50 20 ns t wh sck high time 250 125 40 ns t wl sck low time 250 125 40 ns f sck clock frequency dc 1 dc 3 dc 10 mhz t lz to output low z 50 50 50 ns t ri (1) input rise time 2 2 2 ? ? ? ?????? ????? ?
4 doc. no. 1001, rev. g ::.7: the cat25c32/64 supports the spi bus data transmission protocol. the synchronous serial peripheral interface (spi) helps the cat25c32/64 to interface directly with many of today ? s popular microcontrollers. the cat25c32/64 contains an 8-bit instruction register. (the instruction set and the operation codes are detailed in the instruction set table) after the device is selected with going low, the first byte will be received. the part is accessed via the si pin, with data being clocked in on the rising edge of sck. the first byte contains one of the six op-codes that define the operation to be performed. :7: b )$6 si is the serial data input pin. this pin is used to input all opcodes, byte addresses, and data to be written to the 25c32/64. input data is latched on the rising edge of the serial clock. b 6$6 so is the serial data output pin. this pin is used to transfer data out of the 25c32/64. during a read cycle, data is shifted out on the falling edge of the serial clock.
b "!8 sck is the serial clock pin. this pin is used to synchronize ),6! ") $!"* $ ") wren 0000 0110 enable write operations wrdi 0000 0100 disable write operations rdsr 0000 0101 read status register wrsr 0000 0001 write status register read 0000 0011 read data from memory write 0000 0010 write data to memory :: 06& 1!/")"6,7 # )0 note: dashed line= mode (1, 1) ? ??? valid in v ih v il t css v ih v il v ih v il v oh v ol hi-z t su t h t wh t wl t v t cs t csh t ho t dis hi-z sck si so t ri t fi note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. "+$ # )0 2525 1#%" # >& ) , t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
5 doc. no. 1001, rev. g "!* )$"!* 6, c: c. "!8, "!8, 0 , 0 x 0 protected protected protected 0 x 1 protected writable writable 1 low 0 protected protected protected 1 low 1 protected writable protected x high 0 protected protected protected x high 1 protected writable writable c:.: the communication between the microcontroller and the 25c32/64. opcodes, byte addresses, or data present on the si pin are latched on the rising edge of the sck. data on the so pin is updated on the falling edge of the sck. b/ $! is the chip select pin. low enables the cat25c32/ 64 and high disables the cat25c32/64. high takes the so output pin to high impedance and forces the devices into a standby mode (unless an internal write operation is underway). the cat25c32/64 draws zero current in the standby mode. a high to low transition on is required prior to any sequence being initiated. a low to high transition on after a valid write sequence is what initiates an internal write cycle. bc "! is the write protect pin. the write protect pin will allow normal read/write operations when held high. when is tied low and the wpen bit in the status register is set to 1 , all write operations to the status register are inhibited. going low while is still low will interrupt a write to the status register. if the internal write cycle has already been initiated, going low will have no effect on any write operation to the status register. the pin function is blocked when the wpen bit is set to 0. b"* the pin is used to pause transmission to the cat25c32/64 while in the middle of a serial sequence without having to re-transmit entire sequence at a later time. to pause, must be brought low while sck is low. the so pin is in a high impedance state during the time the part is paused, and transitions on the si pins will be ignored. to resume communication, is brought high, while sck is low.
should be held high any time this function is not being used.) may be tied high directly to v cc or tied to v cc through a resistor. figure 9 illustrates hold timing sequence. 76543210 wpen x x x bp1 bp0 wel ; 6,0 , , 1**,, "! ") "!* 0 0 none no protection 0 1 25c32: 0c00-0fff quarter array protection 25c64:1800-1fff 1 0 25c32: 800-0fff half array protection 25c64:1000-1fff 1 1 25c32: 0000-0fff full array protection 25c64:0000-1fff .
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6 doc. no. 1001, rev. g 06& c:),6! ") # )0 06& c7),6! ") # )0 ; the status register indicates the status of the device. the (ready) bit indicates whether the cat25c32/ 64 is busy with a write operation. when set to 1 a write cycle is in progress and when set to 0 the device indicates it is ready. this bit is read only. the wel (write enable) bit indicates the status of the write enable latch . when set to 1, the device is in a write enable state and when set to 0 the device is in a write disable state. the wel bit can only be set by the wren instruction and can be reset by the wrdi instruction. the bp0 and bp1 (block protect) bits indicate which blocks are currently protected. these bits are set by the user issuing the wrsr instruction. the user is allowed to protect quarter of the memory, half of the memory or the entire memory by setting these bits. once protected the user may only read from the protected portion of the array. these bits are non-volatile. note: dashed line= mode (1, 1) ? ? ? ? note: dashed line= mode (1, 1) ? ? ? ? sk si cs so 00000 110 high impedance sk si cs so 00000 100 high impedance the wpen (write protect enable) is an enable bit for the pin. the pin and wpen bit in the status register control the programmable hardware write protect feature. hardware write protection is enabled when is low and wpen bit is set to high. the user cannot write to the status register (including the block protect bits and the wpen bit) and the block protected sections in the memory array when the chip is hardware write protected. only the sections of the memory array that are not block protected can be written. hardware write protection is disabled when either wp pin is high or the wpen bit is zero. 7=: c )%)*7 ,% the cat25c32/64 contains a write enable latch. this latch must be set before any write operation. the device powers up in a write disable state when v cc is applied. wren instruction will enable writes (set the latch) to thedevice. wrdi instruction will disable writes (reset the latch) to the device. disabling writes will protect the device against inadvertent writes.
7 doc. no. 1001, rev. g 7d6)! the part is selected by pulling low. the 8-bit read instruction is transmitted to the cat25c32/64, fol- lowed by the 16-bit address(the three most significant bits are don ? t care for 25c64 and four most significant bits are don't care for 25c32). after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. the internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. when the highest address (1fffh for 25c64 and fffh for 25c32) is reached, the address counter rolls over to 0000h allowing the read cycle to be continued indefinitely. the readoperation is terminated by pulling the high. to read the status register, rdsr instruction should be sent. the contents of the status register are shifted out on the so line. the status register may be read at any time even during a write cycle. read sequece is illustrated in figure 4. reading status register is illustrated in figure 5. cd6)! the cat25c32/64 powers up in a write disable state. prior to any write instructions, the wren instruction must be sent to cat25c32/64. the device goes into write enable state by pulling the low and then clocking the wren instruction into cat25c32/64. the must be brought high after the wren instruction to enable writes to the device. if the write operation is initiated immediately after the wren instruction without being brought high, the data will not be written to thearray because the write enable latch will not have been properly set. also, for a successful write operation the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block protection level. 06 & *),6! ") # )0 06& 7),6! ") # )0 note: dashed line= mode (1, 1) ? ? ? ? note: dashed line= mode (1, 1) ? ? ? ? sk si so 0000001 1 byte address* 012345678910 2021222324252627282930 7 6 5 4 3 2 1 0 *please check the instruction set table for address cs opcode data out msb high impedance 012345678 10 911121314 sck si data out msb high impedance opcode so 7 6 5 4 3 2 1 0 cs 00 0 00 1 01
8 doc. no. 1001, rev. g 06e& c),6! ") # )0 06& c ),6! ") # )0 note: dashed line= mode (1, 1) e e e e note: dashed line= mode (1, 1) ? ? ? ? sk si so 0 0 0 0 0 0 1 0 address d7 d6 d5 d4 d3 d2 d1 d0 012345678 2122232425262728293031 cs opcode data in high impedance 012345678 10 911121314 sck si msb high impedance data in 15 so cs 7 6 5 4 3 2 10 00 0 000 0 1 opcode 1c once the device is in a write enable state, the user may proceed with a write sequence by setting the low, issuing a write instruction via the si line, followed by the 16-bit address (the three most significant bits are don ? t care for 25c64 and four most significant bits are don't care for 25c32), and then the data to be written. programming will start after the is brought high. figure 6 illustrates byte write sequence. during an internal write cycle, all commands will be ignored except the rdsr (read status register) instruction. the status register can be read to determine if the write cycle is still in progress. if bit 0 of the status register is set at 1, write cycle is in progress. if bit 0 is set at 0, the device is ready for the next instruction. 0c the cat25c32/64 features page write capability. after the first initial byte the host may continue to write up to 64 bytes of data to the cat25c32/64. after each byte of data is received, six lower order address bits are internally incremented by one; the high order bits of address will remain constant. the only restriction is that the 64 bytes must reside on the same page. if the address counter reaches the end of the page and clock continues, the counter will roll over to the first address of the page and overwrite any data that may have been written. the cat25c32/64 is automatically returned to the write disable state at the completion of the write cycle. figure 8 illustrates the page write sequence. to write to the status register, the wrsr instruction should be sent. only bit 2, bit 3 and bit 7 of the status register can be written using the wrsr instruction. figure 7 illustrates the sequence of writing to status register. 7;::7: the cat25c32/64 powers up in a write disable state and in a low power standby mode. a wren instruction must be issued to perform any writes to the device after power up. also,on power up should be brought low to enter a ready state and receive an instruction. after a successful byte/ page write or status register write the cat25c32/64 goes into a write disable mode. must be set high after the
9 doc. no. 1001, rev. g 06f& # )0 06'& 0c ),6! ") # )0 note: dashed line = mode (1, 1) e e e e note: dashed line= mode (1, 1) ? ? ? ? sk si so 0 0 0 0 0 0 1 0 address data byte 1 012345678 212223 24-31 32-39 data byte 2 data byte 3 data byte n cs opcode 7..1 0 24+(n-1)x8-1..24+(n-1)x8 24+nx8-1 data in high impedance cs sck hold so t cd t hd t hd t cd t lz t hz high impedance proper number of clock cycles to start an internal write cycle. access to the array during an internal write cycle is ignored and program-ming is continued. on power up, so is in a high impedance. when powering down, the supply should be taken down to 0v, so that the cat25c32/64 will be reset when power is ramped back up. if this is not possible, then, following a brown-out episode, the cat25c32/64 can be reset by refreshing the contents of the status regis- ter (see application note an10).
10 doc. no. 1001, rev. g notes: (1) the device used in the above example is a 25c64si-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltag e, tape & reel) 7:;:: !80 p = 8-pin pdip s = 8-pin soic u14= 14-pin tssop u20 = 20-pin tssop - > 7( !g 6-- > 25c64 s i te13 "*6! :6#% 25c32: 32k 25c64: 64k $4 te13: 2000/reel $ )0="0 blank = 2.5 to 6.0v 1.8 = 1.8 to 6.0v -1.8 cat #$6)0 blank = commercial (0
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1001 revison: g issue date: 03/29/05 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp a ae 2 a catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company?s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. =:< 7 (& ,") 8/4/2004 f updated features updated dc operating characteristics table & notes 03/29/05 g update reliability characteristics update instruction set - power-up timing

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